Z80 Computer CPU Card (USB Code Loader)

Schematic , Z80 UI , UI Installer 1.00.04 , Help File 001 , FW 01

     Are you ready for some retro computer fun?  This Z80 based computer allows for super fast experimentation without the delay or complexity that PROM/EPROM/EEPROM/NVRAM based systems introduce; no EPROM programmer (Or eraser for that matter!) required, just assemble your code, upload it immediately to the Z80 SRAM and run your program!

     The 1730 uses the Z84C0008VEC processor connected to 64kB of SRAM that serves as both ROM and RAM.  This computer uses a USB interface to upload code from a hex file into the SRAM and after upload, the SRAM can be executed immediately and/or copied into the USB controller's 64kB of SRAM mirroring flash.  If the code was previously copied to flash, after each power cycle the flash is copied back into the SRAM and when the copy process is complete the bus is released, the Reset# signal is de-asserted and the Z80 operates from an 8MHz oscillator, independent of the USB controller.

     The Z80 clock can be supplied from a USB controller SLOW clock from 4Hz to 1kHz or 250kHz, an 8MHz XTAL clock or a SYNTH clock from the USB controller with a frequency range of 1Hz to 16MHz (Waaay over clocked!) with 1Hz resolution. Since this is the CMOS version of the Z80 which is fully static, the processor may also be single stepped and halted by stopping the clock.

     With the USB controller the user also has the ability to do in-circuit-debug (ICD) of Z80 code: After halting the processor, it may be slow or single stepped through the code to observe the program flow using the disassembler built into the UI. The UI also has a 16 register capture window that shows the values of user selected memory addresses when they are written during SLOW clocking or read using the SRAM READ function that makes use of the BUSREQ# signal to the Z80. BUSREQ# can be asserted at which time and any number of bytes from 1 to 65536 can be read directly from SRAM and when done, BUSREQ# is deasserted allowing the code to execute normally... This can be done while operating with any clock source by first stopping the clock.

     For added entertainment an LED signal watcher board can be plugged into the Z80 backplane or in-line with the CPU to examine every Z80 signal in real time.

Hardware Features:

• 3.0 inch wide by 2.5 inch high 4 layer PWB with a 40 pin (2 x 20 x 0.1) edge mounted female connector to mate with the Z80 Backplane or user circuit.
• 8MHz Z84C0008VEC CMOS Z80 CPU: Static operation allows for single stepping.
• 64K of 45nS SRAM for Z80 code execution and data storage.
• 64K of flash memory in the USB controller for SRAM image storage.
• USB connection from the PC/UI to the USB supervisory processor.
• Every pin of the Z80 is connected to the 40 pin connector and are clearly labeled.
• Every pin of the Z80 except for REFRESH# is connect to the USB controller.
• During Z80 code execution, all signals operate transparent to the USB controller unless a WAIT#, RESET# or BUSREQ# is commanded via the UI:  This means the Z80 operates the same as if the USB controller was not there.
• LCD interface mapped to I/O addresses 0xFE (Control) and 0xFF (Data).
• Power is supplied from the USB Mini-B connection (With or without USB data interface) or from the 5V/2A regulator on the backplane (7 to 35V input).

Computer controls:

• A button at the top of the card directly controls the Z80 Reset# signal that operates in parallel with the USB controller (Wired-AND).
• A button is provided on the side of the computer to Start, Stop or single step the computer.
• A button is provided on the side of the computer for future expansion.
• A button is provided on the side of the computer to override the USB controller RESET# operation. (This is labeled "FBL" and is used to force the USB controller into bootload mode. Generally this functionality is not needed as it is mainly for USB controller firmware development).

Memory:

• 64kB of flash in the USB controller (10k write endurance) is provided for non-volatile Z80 code image storage.
• 64kB of SRAM that serves as both the ROM and RAM for the Z80 CPU.
• Upload from the PC to the Z80 computer SRAM can be any number of bytes from 1 to 65536, starting at any address.
• The UI reads in a standard IntelHex file which is formatted for display and prepared for upload to the Z80 computer.  Once loaded, the formatted SRAM image can be saved to a text file.
• Note: The IntelHex file must have the CR+LF line enders to load properly; otherwise an error message will be displayed. The UI help has information on how to easily correct this.
• Uploading 64kB to SRAM takes about 30 seconds (~2kB/S).
• Unused SRAM can be filled with any byte value or left in its uninitialized state to simulate a fully stand alone computer.
• SRAM can be executed by the Z80 immediately after upload without first copying to flash:  A typical, moderately sized program can go from assembler to operation in under 30 seconds.
• If desired, SRAM can be copied to flash after upload is complete, typically in about 30 seconds.
• Code stored in flash will be copied to SRAM at computer power up in under 0.5 seconds and execution started from the 8MHz XTAL clock.
• SRAM can be downloaded from the Z80 computer to the PC and saved as a text file: Download size is any number of bytes from 1 to 65536 bytes starting at any address.
• Downloading 64kB from SRAM takes about 30 seconds (~2kB/S).
• Z80 code execution can be paused, SRAM downloaded and then execution resumed.
• Up and downloading SRAM generates a 32bit CRC:  This allows detection of as little as a single bit change, useful inspect for ROM segment write violations, etc.

Debugging:

• When the Z80 is paused in the BUSREQ#/BUSACK# state, any portion of the SRAM can be downloaded over the serial link.
• When using the SLOW clock at 4Hz to 1kHz or 250kHz, a break-at-address-match can be set which will halt the clock at that location.
• When using the SLOW clock in single step mode or at 4Hz to 1kHz the Z80 code is disassembled in real time. If the windows environment is slower than the Z80 computer bus state report speed, the UI will still capture and disassemble the code, e.g. if the code operates for 10 seconds but windows disassembles at 1/2 the report rate, the disassembly will complete in 20 seconds. Display update throttling is available to improve performance.
• Part of the disassembly process enables the UI to watch for and report writes to any of 16 user specified memory locations while code is running.
• The bus state is only reported when either RD# or WR# are asserted which reduces the RS232 traffic during code execution vs having to report the bus state at EVERY clock cycle.
• Disassembled code can be saved as a test file.
• If the user copies the Z80 registers to SRAM in Z80 code prior to the BUSREQ# assertion the UI can decode that space into a special set of UI registers when that SRAM is read. See UI help file for code example.

Clock sources:

• SLOW clock from the USB controller under UI control operates in single step, 4Hz to 1kHz or 250kHz with break-on-address-match capability. SLOW clock count can be anywhere from 1 to (2^24) cycles and can be canceled from the UI.
• This example is a Real time disassembly with breakpoint of  the LCD driver program (Which also shows the entire upload sequence from scratch) running on the SLOW clock.
• Fixed 8MHz XTAL oscillator.
• SYNTH clock generated by the USB controller from 1Hz to 16MHz with 1Hz resolution.

Accessories:

• A label board is included that fits over the male header pins with signals clearly labeled on both sides.
• The Z80 computer can be run stand alone or can be plugged into the 5 slot Z80 Backplane for hardware expansion.
• The Z80 backplane provides 0 to 2A at 5VDC from a 5.5 x 2.5mm DC jack, reverse polarity protected with an input range of 7 to 35VDC.
• Hardware prototyping is easy with the Backplane Proto Card that has pads on a 0.1 inch grid and space for up to four 40 pin DIPs or many more smaller packages.
• Signals can be examined visually with the Signal Watcher that plugs into the backplane.
• The Piggy Back Signal Watcher has a male header on top and a female connector on the bottom. It can be plugged into the Z80 computer and/or the backplane. An expansion card can be plugged into the piggy back module so it does not waste a backplane slot. The backplane signals can also be probed here.

Firmware/Debug support:

• A free windows Z80 computer control UI is provided to upload code to the Z80 computer, download the computer memory and control the computer hardware.  This UI is also used to update the firmware in the USB controller.
• Sample code:  Z80 Library / zDevStudio Projects. The driver for the LCD interface is included in the Z80 library (LCD Display code timing).
• zDevStudio (SourceForge) is a free Z80 assembler that uses the Pasmo compiler (v0.6).
• The Z80 control UI can reformat the zDevStudio (Pasmo) debug output into a more readable list file with symbol map that can be saved as a text file.
• Loaded IntelHex file data can be saved to a text file in an easy to read 16 bytes per line format with ASCII translation.
  
• Downloaded SRAM data (Or any subset of it) can be saved to a text file in an easy to read 16 bytes per line format with ASCII translation.
• During debug, the user can step through and examine the code execution with the UI using the built in real time Z80 disassembler.