TES Z80 COMPUTER (1730 HW / 032000 FW)	
     The 1730 is a single board Z80 computer stripped down to its essential components: An 8MHz CMOS Z80 processor, 64kB of SRAM that serves as both the ROM and RAM of the system, Clock generation sub-system, Reset control and an LCD interface mapped to I/O ports 0xFE and 0xFF. All signals for the Z80 processor are connected to the 40-pin connector at the bottom of the computer board and are clearly labeled with all of the Z80 signal names. This computer measures 3.0 inches wide by 2.5 inches high.

     Overlaying the Z80 computer is a USB connected microprocessor that has access to every pin of the Z80 which allows it to watch or take over the bus so that the SRAM can be up or down loaded. During Z80 code execution, the USB controller operates transparently to the Z80 processor so that the Z80 operates exactly as it would in a stand alone system. The USB controller has a 64kB flash memory that can store the SRAM image to be loaded back into SRAM at power up; There is no need to store programs in FLASH before running the Z80 as it can execute code from SRAM immediately after the upload is complete. A program can go from assembler to running in a matter of seconds without you ever having to touch the Z80 computer!

The Z80 has a choice of several clock sources:
•	A USB controller SLOW clock from DC to 1kHz or 250kHz.
•	An 8MHz crystal oscillator or FAST clock.
•	A 1Hz to 16MHz programmable FAST clock generated by the USB controller.

     When operating from the SLOW clock between DC (Single Stepping) and 1kHz, the UI will disassemble the code running on the Z80 in real time. This is done by transmitting the bus state whenever the RD# or WR# signals are active which results in a bus state report about once every four clock cycles. When using the SLOW clock at any frequency a software breakpoint can be set that will halt the code when the selected address is encountered.

QUICKSTART GUIDE
1.	Assemble your code and start the Z80 UI.
2.	On the COMM tab, select the port connected to the Z80 computer.
3.	On the UPLOAD tab, click the LOAD HEX button and load in your Z80 code.
4.	On the UPLOAD tab, click the UPLOAD EXTENTS button.
5.	On the CONTROL tab, click the Z80 button.
6.	On the CONTROL tab, click the RSTH button.
7.	On the CONTROL tab, click the CKON button... your code is now running at 8MHz!

CONVENTIONS FOR THIS MANUAL
•	Bracketed [values] indicate user input.
•	Control and tab names are in UPPER CASE regardless of how they appear on the tabs.
•	Some control names may be abbreviated to better fit the formatting of this document.
•	TXD displays the last data transmitted to the Z80 computer.
•	RXD displays the last response from the Z80 computer or the result of the last command (Such as upload completion time) or error messages such as clicking buttons without selecting a COM port.

REVISION HISTORY
REVISION	DATE		DESCRIPTION								
1.00.00	20250617	Initial release

COMM TAB

COMM TAB	The COMM tab controls are used to set up communication with the Z80
	computer as well as handle some housekeeping functions. This tab also
	includes a utility to reformat the zDevStudio debug output into an easy
	to read format with a symbol table. This is where the firmware update
	utility (TESBLC) to reprogram the USB controller can be accessed.

DISP Z80 HELP	Displays this help file which is also available as a wordpad document in the
	installation directory.

PORT	Selects the serial port for communication with the Z80 computer: On startup
	the application checks for connected Z80 computers. Pressing ENTER in
	the port list rescans for connected Z80 computers and pressing SPACE
	scans for all available ports.

PING	Checks communication with the computer USB controller: The typical
	response is !0003200rr[cr] where rr is the firmware revision.

RESET?	Reset source for the USB controller.

RESET!	Force the USB controller to do a power on reset. This will also force the
	reload of the SRAM from FLASH if an image is available in FLASH.

RESCAN	Close the serial port an re-scan for connected computers.

FW UPDATE	Opens a window to enable updating the Z80 computer USB controller
	firmware.

ENABLE CNTRLS	If the SLOW clock does not complete normally such as when the computer
	loses power during clocking, this allows the controls to be reenabled:
	When SLOW clocking, all but the STOP controls are disabled to prevent
	interference with the SLOW clock processing.

PASTE ZDEV	Paste a zDevStudio debug listing and process it into a formatted listing with
	a symbol map.

SAVE LIST FILE	Save formatted listing to a text file.

?	Display help for the zDevStudio debug listing conversion procedure.

UPLOAD TAB

UPLOAD TAB	The UPLOAD tab controls allow the user to read in IntelHex code files
	and then upload the data to the Z80 computer SRAM. Once the code has
	been uploaded it can be committed to FLASH within the USB control
	processor which will copy the code to SRAM after a power cycle. Data
	read and formatted can be saved in a text file.

UPLOAD DISP	This contains the formatted data loaded from an IntelHex file and is always 
	64kB deep regardless of the number of bytes in the file. Any bytes that
	are not explicitly defined in the hex file are represented by the large dot and
	any byte that is unprintable is represented as a small dot in the ASCII table
	to the right of the hexadecimal byte data.

LOAD HEX	Load an IntelHex code file into UI memory.

SAVE	Save the loaded and formatted hex file data to a text file.

FBYT	Address of first byte loaded from the IntelHex file.

LBYT	Address of last byte loaded from the IntelHex file.

RBYT	Number of bytes explicitly loaded from the IntelHex file. The flyover help
	also shows the percentage size of the read block vs the 64kB total.

UPLOAD ALL	Upload the entire 64kB UI memory to the Z80 computer SRAM. Bytes not
	explicitly defined in the hex file will be filled with the UF byte value.

UPLD EXTENTS	Only bytes defined by the hex file in the address range of FBYTE to LBYTE
	are uploaded into the Z80 computer SRAM. Any bytes within this address
	range not explicitly defined by the hex file will be filled with the UF byte value.

UPLOAD BLOCK	Upload the block between USTR and UEND from the UI memory to the Z80
	computer SRAM. Any bytes not defined by the hex file are filled with the UF
	byte value.

[USTR] to [UEND]	Block start and end addresses in hexadecimal. Any number of bytes from 1 to 
	65536 may be uploaded to SRAM starting at any address.

[UB]	Bytes that are not defined by the hex file are filled with this hexadecimal value.

UCOUNT	The number of bytes in decimal uploaded to the Z80 computer SRAM. The
	flyover help also shows the percentage size of the read block vs the 64kB total.

UCRC	CRC32 hash of the bytes uploaded to SRAM.

CMMT TO FLASH	The SRAM contents are copied into the USB controller FLASH, matching the
	start, end and size parameters of the last upload.

FILL ALL SRAM	All 64kB of the Z80 computer SRAM are loaded with the FB hexdecimal value.

FILL BLOCK	Bytes from FSTR to FEND of the SRAM are loaded with the FB value.

[FB]	SRAM is filled with this hexadecimal value.

[FSTR] to [FEND]	Hexadecimal fill address limits. Any number of SRAM bytes from 1 to 65536
	may be filled with the FB value, starting at any address.

CRC	The CRC32 hash of the bytes uploaded to SRAM from the UI memory.

SIZE	Number of bytes uploaded to SRAM from the UI memory. The flyover help
	also shows the percentage size of the upload block vs the 64kB total.

CONTROL TAB

COTROL TAB	The CONTROL tab controls are used to execute code that has been
	uploaded to the Z80 computer SRAM as well as to display and save
	the results of the disassembly process. 

OPCODE DISP	The results of the real time disassembly are shown here with the first
	opcode at the top of the display.

CONTROL DEC	The reported state of the Z80 address and data bus plus all of the control
	signals are parsed out into this window.

USB	Sets the Z80 bus to be under the control of the USB processor.

Z80	Releases the Z80 bus to operate normally.

RSTL	The Reset# signal on the computer is driven low and 32 clocks are sent
	to the Z80 to ensure it is fully in the reset state.

RSTH	The Reset# signal on the computer is driven low followed by 32 clocks and
	then released high (Open drain) to take the Z80 out of reset.

CKON	Switches the FAST clock into the Z80 processor.

CKOFF	Disables the FAST clock sets the Z80 clock input is set to a
	logic zero.

CLK1	A single SLOW clock pulse is generated.

CLKN	The CLKSOUT number of SLOW clocks will be sent to the Z80.

[CLOCKSOUT]	This is the decimal number of SLOW clocks from 1 to (2^24)-1 = 16777215.
	When CLKN is running, this displays the current count down and when done
	or cancelled the user input is restored.

[PERIOD]	The SLOW clock period, i.e.time for a full high to low clock cycle. 

[ACC]	When checked, the clocks reported in CLKSIN are accumulated and when
	unchecked CLKSIN is equal to the last number of SLOW clocks reported.

[CLOCKSIN]	Number of SLOW clocks actually sent to the Z80. This will be less than
	CLKSOUT if the user hits the stop button or a breakpoint is reached.

[N]	When operating at high clock rates, the refresh of the OPCODE DISPLAY
	may slow down the update causing a lag in the disassembly vs the operation
	of the computer. To speed up processing, the display can be refreshed at
	a lower rate than the incoming bus state reports. For instance, setting N to 
	10 refreshes the OPCODE DISPLAY once for every bus report.

STOP	The SLOW clock sequence may be cancelled by the user by hitting the STOP
	button. You will notice that when executing a CLKN command, all of the other
	controls are disabled, i.e. STOP is the only available command.

SETBP	Sets the break point in the computer.			

CLRBP	Clears the breakpoint by setting it to 0x0000: 0x0000 is the only address at
	which a breakpoint can't be set.

GETBP	Reads the current breakpoint.

[BKPOINT]	The breakpoint may be any hexadecimal value from 0001 to FFFF.

OPCODES SAVE	Saves the OPCODE DISPLAY window to a text file.

OPCODES CLS	Clears the OPCODE DISPLAY window and sets the CLKSIN value to zero.

SHOW CAPTURE	This pops out a small windows that allows data written to specific addresses
	to be captured, either during the SRAM read functions or during the Z80 real
	time disassembly from the CONTROL tab.

SRAM TAB

SRAM TAB	The SRAM tab controls allow the user to download (Read) the data
	stored in the Z80 computer SRAM. Once read, the data can be saved to
	a text file.

SRAM DISP	SRAM is displayed in 16 byte blocks with the ASCII translation shown to
	the right of the hexadecimal byte data. Unread bytes within each line are 
	represented by large dots and unprintable characters are represented by
	small dots in the ASCII section.

READ ALL SRAM	Reads all 64kB of SRAM from the Z80 computer.

READ BLOCK	Reads a block of SRAM from RSTR to REND.

[RSTR] to [REND]	Memory range to read in hexadecimal. This can be of any number of bytes
	from 1 to 65536 starting at any address.	

BUSREQ# LOW	For all clocking modes, this asserts the BUSREQ# signal to the Z80 and waits
	for the Z80 to assert BUSACK#. When in this state, the SRAM may be read
	or written to. Note that if the mode is already LOW pressing this button has no
	effect. 

BUSREQ# HIGH	This command deasserts the BUSREQ# signal to the Z80 and when the Z80
	has responded by deasserting the BUSACK# signal the clock may be again
	enabled and code execution resumed. Note that if the mode is already HIGH
	pressing this button has no effect. 

SAVE SRAM	Saves the formatted SRAM data to a text file.

SHOW CAPTURE	This pops out a small windows that allows data written to specific addresses
	to be captured, either during the SRAM read functions or during the Z80 real
	time disassembly from the CONTROL TAB.
 
CRC32	A CRC32 hash of the bytes read is displayed here.

SIZE	The decimal count of the bytes read is displayed here. The flyover help
	also shows the percentage size of the read block vs the 64kB total.

CAPTURE POP OUT

CAPTR POP OUT	The CAPTURE POP OUT (Activated from the SRAM tab) allows the user to
	decode up to 16 specific memory 	locations to simplify code debug. In the
	SRAM tab, when a read is done and any of the addresses in the table are
	encountered its value will be placed in the table and the background color set
	to green, the previous capture will have its background reset to white. This
	operates the same during the real time disassembly in the CONTROL tab
	whenever a listed memory address is written to (WR# active).

[A],[B] etc	These are user defined lables for the SRAM capture function. These can be
	between 1 and 11 alpha numeric characters without spaces.  This example 
	displays all of the internal registers written to memory locations 0x8000 to 
	0x800F using the 16 bit data writes (Hence the addressing order).  Example
	of this code is shown below.

[8000],[8001] etc	These are addresses that are searched for during SRAM reads or real time
	disassembly writes and are in hexadecimal from 0x0000 to 0xFFFF. When
	set to 0x0000, this tells the software to skip this table item in the search.	

SAVE MAP	Saves the capture labels, addresses and data to a "xxx.MAP" text file.

LOAD MAP	Loads the capture table from a "xxx.MAP" text file.

CLEAR ALL	Clears the capture addresses to 0x000 and clears the captured data to "--".

CLEAR DATA	Clears the captured data to "--".

;Example Z80 code to save all of the internal registers to memory locations
;that can then be captured during and SRAM read or real time disassembly.
saveregs:	Push	bc	;Save current BC to stack
	Push	af	;Save current AF to stack
	ld	(0x8002),bc	;Save current BC to SRAM
	pop	bc	;Get AF from stack and put it into BC
	push	bc	;Save current BC as AF to the stack
	ld	(0x8000),bc	;AF popped from stack and saved to SRAM
	ld	(0x8004),de
	ld	(0x8006),hl
	ld	(0x8008),ix
	ld	(0x800A),iy
	ld	a,r	;Low byte of register pairs saved to first address
	ld	(0x800C),a
	ld	a,i
	ld	(0x800D),a
	ld	(0x800E),sp
	pop	af
	pop	bc
	ret

TEST TAB

TEST TAB	The controls on the TEST TAB are used for computer test and program
	verification. Many of these controls are duplicated on the CONTROL TAB.

BUS = USB	This button sets the Z80 bus to be under the control of the USB processor.

BUS = Z80	This button releases the Z80 bus to operate normally.

RST# L	The Reset# signal on the computer is drive low.

RST# H	The Reset# signal on the computer is released high (Open drain).

RST# L+CLK	The Reset# signal on the computer is driven low and 32 clocks are sent
	to the Z80 to ensure it is fully in the reset state.

RST# L+CLK+H	The Reset# signal on the computer is driven low followed by 32 clocks and
	then released high (Open drain) to take the Z80 out of reset.

RESET?	The state of the reset control out of the USB controller is querried. A high
	indicates the open drain driver is switched on which results in the Reset#
	into the Z80 bein driven low.

8MHZ CLK ON	This button switches the FAST clock into the Z80 processor.

8MHZ CLK OFF	This button disables the FAST clock sets the Z80 clock input is set to a
	logic zero.

CLK1	A single SLOW clock pulse is generated.

CLKN	The CLKSOUT number of SLOW clocks will be sent to the Z80.

[CLKSOUT]	This is the decimal number of SLOW clocks from 1 to (2^24)-1 = 16777215.
	When CLKN is running, this displays the current count down and when done
	or cancelled the user input is restored.

[PERIOD]	The SLOW clock period, i.e.time for a full high to low clock cycle.	

STOP	The SLOW clock sequence may be cancelled by the user by hitting the STOP
	button. You will notice that when executing a CLKN command, all of the other
	controls are disabled, i.e. STOP is the only available command.

BUSREQ# LOW	For all clocking modes, this asserts the BUSREQ# signal to the Z80 and waits
	for the Z80 to assert BUSACK#. When in this state, the SRAM may be read
	or written to. Note that if the mode is already LOW pressing this button has no
	effect. 

BUSREQ# HIGH	This command deasserts the BUSREQ# signal to the Z80 and when the Z80
	has responded by deasserting the BUSACK# signal the clock may be again
	enabled and code execution resumed. Note that if the mode is already HIGH
	pressing this button has no effect. 

Z80DIS TEST 1	This button calls a function in the Z80 Disassembly library that reads in a test
	vector file and then verifies that the disassemblly logic returns the correct 
	result for fully formed opcode sequences.

Z80DIS TEST 2	This button calls a function in the Z80 Disassembly library that reads in a test
	vector file and then verifies that the disassemblly logic returns the correct 
	result for each successive byte of and opcode sequence: It should return
	nothing until the opcode sequence is fully formed.

TRBUFFER CLR	The RS232 trace buffer is cleared.

TRBUFFER SAVE	The RS232 trace buffer is saved to a text file

[EN]	When checked, all RS232 outgoing and incoming traffic is logged to a buffer
	that can then be saved for examination. Transmit data is time stamped and
	added to the buffer as is where only received data frames (!....[cr]) are time-
	stamped and saved to the trace buffer.

RS232 PROTOCOL
     The 1730 USB controller uses a serial protocol based on frames, where the start of a command frame (From the UI to the 1730) begins with a "$" character and ends with the [cr] character. Ending a frame with [cr][lf] (Or [nl] = NewLine) does not affect the processing of these frames because all characters outside of the "$....[cr]" sequence are discarded, however when using a terminal program using the [nl] sequence can make the terminal output more readable. Response frames (From the 1730 to the UI) start with a "!" character and end with either a [nl] sequence or with just a [cr] character. The shorter end sequence is used where throughput is at a premium. All data sent to the 1730 computer is in ASCII hex with even numbers of hex characters; sending the command $0010F[cr] will result in a low level response of !00f[cr]. The communication protocol is 115200,n,8,1.

Command/Response structure										
$UUCCdd...dd[cr]	UU		Unit ID, always 00
	CC		Command ID, 00 to FF
	dd...dd	Variable length command data, from 0 to 254 bytes
			254 bytes is 508 ASCII hex characters, converted to bytes
			on the fly as the character pairs are received.
!UUCCx	UU		Unit ID, always 00
!UUCCdd...dd[cr]	CC		Command code, 00 to FF
	x	a	Ack response when no data bytes are required
		n	Nack response, supplied data did not pass for range testing
	 	f	Framing error, i.e. to few/many data bytes, uneven hex count
		?	Command does not exist
		(x)	See commands for other single character responses

Command/Response	Command/Parameters							
$0000[cr]		Device identification
!00032000rr[nl]		rr	Firmware revision

$0006[cr]		Reset cause for USB controller
!0006rr[nl]		rr	Reset cause

$0007[cr]		Forced reset
!0007a[nl]		a	Ack

$0010mm[cr]		Z80 Reset# control
!0010a[nl]		mm	00	Reset = Low, Reset# = High
!0010rr[nl]			01	Reset = High, Reset# = Low
			FF	Report Reset state
		a	Ack
		rr	00	Reset = Low, Reset# = High 
			01	Reset = High, Reset# = Low

$0011mmccccccdd[cr]	Set Z80 clock control	
!0011x[nl]		mm	00	Clock is Low (Off)
			01	Clock is 8MHz FAST clock
			02	Verbose SLOW clock with cc...ccdd params
			03	Silent SLOW clock with cc...ccdd params
			cc.cc	24 bit SLOW clock count
			dd	SLOW clock period in mS
		x	a	Ack
			d	SLOW clock completed
			b	SLOW clock breakpoint encountered

$0012mm[cr]		Set SRAM bus control mode
!0012a[nl]		mm	00	Bus is controlled by Z80
			01	Bus is controled by USB controller
			FF	Report current bus control mode
			a	Ack

$0020nnaaaadd.dd[cr]	Write to SRAM (Bus control mode is set to USB)
!0020a[nl]		nn		Number of bytes to write+1: 00 to 7F=01 to 80
		aaaa		Starting address of write (No wrap around after FFFF)
		dd.dd		Data bytes, always 128 regardless of nn
		a		Ack

$0021nnaaaa[cr]		Read bytes from SRAM
!0021nndd.dd[nl]		nn		Number of bytes to read+1: 00-FF=01 to 100
		aaaa		Start address of read (No wrap around after FFFF)
				Bytes after 0xFFFF are returned as large dot char
		dd.dd		1 to 256 bytes of SRAM data

$0022nnnnaaaadd[cr]	Fill SRAM with data
!0022a[nl]		nnnn		Number of bytes+1: 0000 to FFFF=0001 to 10000
		aaaa		Start address of fill (No wrap around after FFFF)
		dd		Data to fill SRAM with
		a		Ack

$0030nnaaaadd.dd[cr]	Write to FLASH (SRAM image storage in the USB controller)
!0030a[nl]		nn		Number of bytes to write+1: 00 to 7F=01 to 80
		aaaa		Starting address of write (No wrap around after FFFF)
		dd.dd		Data bytes, always 128 regardless of nn
		a		Ack

$0031nnaaaa[cr]		Read bytes from FLASH
!0031nndd.dd[nl]		nn		Number of bytes to read+1: 00-FF=01 to 100
		aaaa		Start address of read (No wrap around after FFFF)
				Bytes after 0xFFFF are returned as large dot char
		dd.dd		1 to 256 bytes of FLASH data

$0032xxxxyyyy[cr]		Erase FLASH
!0032nnnn[nl]		xxxx		Start address, 0000 to FFFF
!0032d[nl]		yyyy		End address, 0000 to FFFF
!0032n[nl]		nnnn		Count reported for every 4096 bytes erased
		d		Erase is done
		n		Nak because start was greater than end address

$0040bbbb[cr]		Set a breakpoint
!0040a[nl]		bbbb		Breakpoint address from 0001 to FFFF
				0000 = No breakpoint is set
		a		Ack

$004F[cr]		Read back current breakpoint
!004Fbbbb[nl]		bbbb		Breakpoint address

$Fssnnnnnnaaaaddccc[cr]	Bus state report while SLOW clocking ($0011)
		ss		Response sequence count
		nnnnnn	24 bit SLOW clock cycle countdown
		aaaa		Z80 address
		dd		Z80 data
		ccc		Z80 control lines, e.g. RD#, WR# etc
				Same order as the CONTROL tab CONTROL DEC
				MSB = BACK#, LSB=RSET#
				Note that if Reset# is low at start, task is terminated
				with a reported 000000 clocks

!Essnnnnnn[cr]		Slow clock cycle countdown report when PERIOD = 0 ($0011)
		ss		Response sequence count
		nnnnnn	24 bit SLOW clock cycle countdown
				Only reported every 50mS

!Dssnnnnnn[cr]		Slow clock end of task cycle report ($0011)
		ss		Response sequence count
		nnnnnn	24 bit SLOW clock cycle count
				May be less than commanded clocks if user cancel
				or breakpoint detection terminated the task

TESBLC (USB CONTROLLER FW UPDATE UTILITY)

TESBLC	Activated from the COMM tab of the main UI, the TESBLC utility is
	used to update the firmware in the 1730 USB controller.  Follow the
	steps below to accomplish this. The bootloader in the 1730 is very 
	robust and can recover from many fault situations such as power 
	loss, port disconnection or incorrect firmware image upload.

1.	Open the COM port connected to the 1730 computer.  Note that all ports are listed
	in this utility as a device may not be the application mode thereby preventing PING 
	method to identify it. (Note than the baud rate is automatically selected for the 1730)

2.	Click the PING button. If the 1730 is connected, the response will be !00032000rr[cr]
	if in the application, or !Bf[cr] if the bootloader it running; this is a framing error
	response to the $0000[cr] ping querry.	

3.	If in the application mode, click the APP WRITE button and select the code hex file.

4.	If in the bootloader mode, blick the BOOT WRITE button and select the code hex
	file.

5.	If the process completed normally, the 1730 in the application mode will respond as
	in (2) with the PING response sent when the device reboots.

6.	If the process was interrupted, the 1730 will remain in the bootloader and the update
	can be reattempted per step 4.

7.	If an unrecoverable error occurs, the SAVE TRACE BUFFER button can be used to 
	save the RS232 traffic for analysis.
		
1730 Z80 COMPUTER HARDWARE

P1	All Z80 signal 40-pin connector. Can be plugged into a 1731 backplane or a 1733
	signal watcher board.

P2	USB Mini-B connector for UI control and 5V power.

P3	(Bottom of board) ICSP connection to the USB controller.

P5	8 bit LCD interface connector.

R30	Contrast setting for the LCD.

D2	Monitor LED, signals that the USB controller background processing is operating.
	Typical blink rate is 5Hz. Accuracy of the internal clock can be measured here.

SW1	This drives the Z80 Reset# signal low (Wired-AND with the USB controller Reset#
	functionality.

SW2	Forced Boot Load switch. If pressed during power up it forces the USB controller to
	enter boot load mode. This is used during FW development to prevent application
	code with errors such as infinite loops from disabling the boot load function.

SW3	Manual clock control

SW4	Future feature

U1	Z84C0008 8MHz CMOS microprocessor.

U2	Lower 32kB SRAM, address space 0x0000 to 0x7FFF.

U3	Upper 32kB SRAM, address space 0x8000 to 0xFFFF.